1. Field of the Invention
The present invention generally relates to a pad structure of a semiconductor device, and more particularly to a multilayer pad structure of the semiconductor device in which a plurality of pad layers including the copper wirings formed with the damascene process are provided and reliability for mechanical stress has been improved.
2. Description of the Related Art
In recent years, a semiconductor device is more and more reduced in size of the design rule of wiring with accompaniment of further improvement in miniaturization and high packing density. A multilayer wiring structure consisting of copper (Cu) wiring has been employed corresponding to such tendency. The multilayer wiring formed of copper wiring is realized with the damascene process. Namely, a copper multilayer wiring is formed through the known process in which via holes are formed in an insulating film in order to connect grooves for wiring and wirings, the grooves and via holes are filled with copper, and copper adhered to the regions other than the grooves and via holes is removed with the chemical-mechanical polishing (CMP) process.
With the use of a multilayer wiring structure using copper wiring, a multilayer pad structure including the pad layer including the copper wiring formed with the damascene process which is similar to the copper multilayer wiring is also employed in the pad used for connection with various electrical signal lines from external system (data signal line, control signal line, and power source potential supply line or the like). For example, refer to Japanese Laid-Open Patent Application No. 2003-086589, Japanese Laid-Open Patent Application No. 11-150114, and Japanese Laid-Open Patent Application No. 10-229085.
FIG. 1 illustrates a multilayer pad structure including a pad layer which has copper wiring in a conventional device. In FIG. 1, (a) is a cross-sectional view of a copper pad layer (single layer), and (b) is a plan view of the copper pad layer. Only the pad region is illustrated and an internal circuit region is not illustrated.
In FIG. 1: reference numeral 11 denotes a semiconductor substrate; 12 denotes a pad layer; 13 denotes a wiring region constituting the pad layer; 14 denotes an intralayer insulating region provided in the wiring region 13; 15 denotes an interlayer insulating film; 16 denotes a via provided in the interlayer insulating film; and 17 denotes a cover film.
As illustrated in FIG. 1, the conventional multilayer pad structure is formed by laminating a plurality of pad layers 12 on the semiconductor substrate 11 via the interlayer insulating film 15 formed of a silicon oxide film. The cover film 17 is formed on the interlayer insulating film 15. This cover layer 17 is not formed on the pad layer 12, but an aperture is formed. A lead wire is connected to the uppermost layer 12a of the pad layer exposed at the aperture with the wire bonding method in the assembling process and a probe stylus is also in contact thereto in the test process for inspecting electrical characteristics of semiconductor device.
The uppermost layer 12a among the plurality of pad layers is formed of an aluminum (Al) wire. The remaining pad layers 12b and 12c are formed of a wiring region 13 of copper (Cu) and a plurality of intralayer insulating regions 14 of silicon oxide film allocated within the copper wiring region 13. Each pad layer is connected with a plurality of vias 16 provided in the interlayer insulating film 15. The plurality of vias 16 connects the aluminum wire of pad layer 12a and the copper wiring region 13 of the pad layer 12b and also connects the copper wiring regions 13 of the pad layers 12b, 12c to set up electrical connection among a plurality of pad layers. The plurality of vias 16 are formed of tungsten (W).
In FIG. 1, (b) illustrates the wiring layout of the pad layers 12b, 12c. The pad layers 12b, 12c have the identical wiring layout. As illustrated in FIG. 1, the pad layers 12b, 12c have the rectangular external wirings and a mesh type wiring structure ensuring constant lines and spaces is provided within the external wiring. That is, the copper wiring region 13 of the pad layers 12b, 12c forms the mesh type copper wiring network. Within the external wiring of the pad layers 12b, 12c, a plurality of rectangular intralayer insulating regions 14 are regularly allocated in the layout of constant pitch in the vertical and horizontal directions corresponding to the mesh type wiring structure.
In the pad layers 12b and 12c, a plurality of intralayer insulating regions 14 are provided in the internal portions thereof and the mesh type wiring structure is created, so that the restrictions for a maximum width of the copper wiring and a maximum occupation ratio of the copper wiring per unit area are satisfied. Thereby, influence of the dishing phenomenon in the CMP process can be lowered.
In the conventional pad structure of FIG. 1, since the copper pad layers 12b, 12c except for the uppermost layer 12a have the identical wiring layout, the region not covered with the copper wiring is generated within the region in the lower layers of the uppermost layer 12a when the pad region is perspectively viewed from the perpendicular upper direction for the semiconductor substrate 11. In other words, when the semiconductor substrate is perspectively viewed from the perpendicular upper direction, the region which is covered only with an insulating film is generated in the pad region except for the aluminum wiring of the uppermost layer 12a. 
Since an insulating film, such as a silicon oxide film (SiO2 film), is more soft than a metal material used for the wiring layer such as copper (Cu), the following problems (1) and (2) may arise when mechanical stress is applied to the pad from external side during the processes such as probing (touch of stylus) in the test process and wire bonding in the assembling process.
(1) In the portion of the pad region, a structure in which only a plurality of insulating films, such as the intralayer insulating region 14 and the interlayer insulating film 15 within the pad layer 12, are laminated as indicated by the dotted lines in FIG. 2. Therefore, if crack is generated in the insulating films of the upper layers of the multilayer pad due to externally applied mechanical stress, it is easily extended up to the insulating films of the lower layers or to the insulating films of the lower layer region of the multilayer pad as illustrated in FIG. 2.
If crack is continuously generated for a plurality of layers as described above, a problem in which water invades into the lower layer regions of the multiplayer pad via the crack. Thereby, reliability of the semiconductor device may be remarkably lowered.
(2) In the portion of the pad region, since only the insulating film is provided, except for the aluminum wiring in the uppermost layer, as the material for alleviating the externally applied mechanical stress, this stress is transferred in direct to the lower layer regions of the multilayer pad without attenuation. Accordingly, the lower layer regions of the multilayer pad may be damaged due to the externally applied mechanical stress, and thereby reliability of the semiconductor device is also remarkably lowered.
Particularly when the semiconductor elements, such as a transistor and connection wiring which form an input/output (I/O) circuit, are formed in the lower layer region of the multilayer pad, these semiconductor elements and wires are broken by the mechanical stress and thereby defective operation is generated in the input/output circuit.
In order to overcome the above problems (1) and (2), the counter-measure for increasing a coverage rate of the copper wiring when viewed perspectively from the perpendicular upper direction by expanding the area of the copper wiring region 13 within the pad layer 12 exceeding the restrictions for the maximum width of the copper wiring and the maximum occupation rate of the copper wiring per unit area cannot be taken because such counter-measure will increase the influence of the dishing phenomenon in the CMP process.